1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a multi-bit serial-in or serial-out function and a bit structure switching function.
2. Description of Related Art
In conventional semiconductor memory devices having a multi-bit serial-in and serial-out function, a bit structure has been fixed for each one of products. However, with increase of the bit number in this type of memory, it has become necessary to provide a function for switching the bit structure through an external input.
FIGS. 1A, 1B and 1C show, in combination, a semiconductor memory device in which the above mentioned bit structure switching function is realized by using shift registers included in this type of conventional semiconductor memory device.
In FIGS. 1A, 1B and 1C, Reference Signs "RB" and "RC" designate a shift register, and Reference Sign "SA" shows a selector. In order to determine an address of a memory cell to be read or written, the selector "SA" selects the output of which of the two shift registers "RB" and "RC" should be used.
In FIGS. 1A, 1B and 1C, Reference Numerals 6, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34, 37, 38, 41, 42, 45, 46, 49, 50, 53, 79, 82, 83, 86, 87, 90, 91, 94, 95, 98, 99, 102 and 109 to 120 designate a transfer gate. Reference Numerals 1, 2, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39, 40, 43, 44, 47, 48, 51, 52, 57, 61, 65, 69, 73, 77, 78, 80, 81, 84, 85, 88, 89, 92, 93, 96, 97, 100, 101, 104, 106 and 108 indicate an inverter. Reference Numerals 56, 60, 64, 68, 72, 76, 103, 105 and 107 show a NAND gate.
Now, operation of the conventional example will be explained with reference to a timing chart of FIG. 2. For simplification of the explanation, it is assumed that outputs OUT1 to OUT6, OUT12, OUT34 and OUT56 of the shift registers "RB" and "RC" have been initialized to a ground level (called a "low level" hereinafter).
It is continued that the low level and a voltage supply voltage (called a "high level" hereinafter) are periodically alternately supplied as a shift register control signal CLK1. If a shift register input signal IN is brought to a high level only during the period of a certain cycle of the clock CLK1, the first shift register outputs OUT1 and OUT12 are brought to a high level in the same cycle. When CLK1 goes into a next cycle, the first shift register outputs OUT1 and OUT12 are brought to a low level, and the second shift register outputs OUT2 and OUT34 are brought to a high level. Similarly, in the following, at each time the clock CLK1 advances its cycle, information of a shift register input signal IN is sequentially transferred through the shifter registers, from OUT1 to OUT2, and then, from OUT2 to OUT3, and so on.
At this time, if a bit structure control signal MODE is at a low level, a memory selection signal YSW1 of memory selection signals YSW1 to YSW6 is firstly brought to a high level, so that a group of memory cells selected by the memory selection signal YSW1 are activated. In the next cycle, the memory selection signal YSW2 is brought to a high level, so that a group of memory cells selected by the memory selection signal YSW2 are activated. On the other hand, when the bit structure control signal MODE is at a high level, the memory selection signals YSW1 and YSW2 are firstly brought to a high level, so that groups of memory cells selected by the memory selection signals YSW1 and YSW2 are activated. In the next cycle, groups of memory cells selected by the memory selection signals YSW3 and YSW4 are activated. Accordingly, when the bit structure control signal MODE is at a high level, it is possible to activate the memory cell groups that are two times the memory cell groups) activated when the bit structure control signal MODE is at a low level. Therefore, it is possible to change the bit structure from a 4-bit structure to a 8-bit structure, or alternatively, from the 8-bit structure to a 16 -bit structure.
The above mentioned conventional bit structure switching circuit requires a plurality of shift registers of the number corresponding to the number of the bit structures to be switched over, and also needs a selector for controlling on the basis of the output of which of the plurality of shift registers the memory cell selection should be performed. Accordingly, the above mentioned conventional bit structure switching circuit requires an increased number of circuit constituents, and therefore, needs a greatly increased chip area when the circuit is implemented in an integrated circuit.